Existing analog and mixed-signal (AMS) electronic design automation (EDA) tools, such as the VHDL-AMS and Verilog-AMS languages, have the capability to work with only pure VHDL-AMS or pure Verilog-AMS designs respectively. A detailed description of working with pure VHDL-AMS designs is found in “IEEE Standard VHDL Analog and Mixed-Signal Extensions,” published by IEEE-SA Standards Board on Dec. 23, 1999. A detailed description of working with pure Verilog-AMS designs is found in “Verilog-AMS Language Reference Manual—Analog & Mixed-Signal Extensions to Verilog HDL” (Verilog-AMS LRM) published by Accellera International Inc. on Jan. 20, 2003. However, circuit designers are interested in working with design components from both languages, and do not want to be constrained to either the VHDL-AMS language or the Verilog-AMS language.
A challenge in a mixed-language mixed-signal design is to integrate design components of different signal types into one common design. FIG. 1 illustrates an example of a design that consists of digital and analog signal types. The top level Verilog-AMS design 100 includes two instances I1 and I2. The instance I1 102 has a digital port 104 while the instance I2 106 has an analog port 108. The top level Verilog-AMS design further includes an analog net ‘a’ 110, which may be used to connect the ports of instances I1 and I2. However, due to the incompatibility between the digital port 104 and the analog port 108, a mechanism is needed to bridge between the ports of the two instances I1 102 and I2 106.
The Verilog-AMS language provides a capability to connect between an analog instance and a digital instance. In order to do so, a connect module (CM) is inserted between the respective ports of the instances either manually by the user or automatically by an analog and mixed-signal EDA tool. FIG. 2 illustrates a connect module inserted between the two incompatible instances of FIG. 1. In addition to the instances I1 102 and I2 106, and their corresponding ports 104 and 108, the top level Verilog-AMS design 200 includes a connect module 202, a digital port 204, and an analog port 206. The analog port 206 is configured to connect to the analog port 108 of the instance I2 108. Upon inserting the connect module 202, the digital drivers from the digital port 104 of instance I1 102 are segregated from the digital receivers of the digital port 104. This approach is referred to as driver-receiver segregation (DRS) or segregating driver and receiver (SDR).
One of the problems in supporting a mixed-language mixed-signal design lies in the lack of compatibility between the VHDL-AMS and Verilog-AMS languages. There are a number of incompatibilities between the Verilog-AMS and VHDL-AMS languages. One such incompatibility is the lack of support for the driver-receiver segregation (DRS) methodology by the VHDL-AMS language. The DRS allows accurate modeling of the effects of analog interconnects on digital signal propagation. As shown in FIG. 2, when an analog net is directly connected to a digital net in a Verilog-AMS design, a connect module (CM) is inserted. The CM includes at least one digital port and one analog port. When the CM is inserted between the analog and digital nets, the digital port of the CM is connected to the digital net and the analog port of the CM is connected to the analog net. In this way, Verilog-AMS ensures that digital nets are always connected to other digital nets only and analog nets are connected to other analog nets only. As a part of this DRS process, the digital drivers are segregated from the digital receivers.
There are a number of approaches utilized to address these issues in an MLMS design. One approach is to create a Verilog-AMS wrapper around the VHDL-AMS block such that the connection between this Verilog-AMS wrapper and the VHDL-AMS block are in the same domain. The DRS is then performed within the Verilog-AMS environment. One drawback of this approach is that the user has to know where such connections exist in a design. In a System-On-a-Chip (SOC) design, there can be thousands of such connections. The wrapper modules need to be created manually or using a wrapper tool like NCShell, developed by Cadence Design Systems, Inc. However, the process of identifying these blocks and implementing the fixes or workarounds for such connections consumes a lot of time and effort.
Another approach is to define the Verilog-AMS net that connects to VHDL-AMS net as a domainless net (i.e. nets without a domain or discipline), then the discipline resolution technique is applied to coerce (force) the Verilog-AMS net to be of the same domain as the VHDL-AMS net. However, this approach does not work if a given Verilog-AMS domainless net is connected to both a VHDL-AMS analog net and a VHDL-AMS digital net.
In addition to the limitations described above, other differences between Verilog-AMS and VHDL-AMS languages also impose challenges in implementing DRS in a mixed-language mixed-signal environment. First, the VHDL-AMS language, being a strongly typed language, does not allow connections between analog and digital nets. However, in a mixed-language mixed-signal design, there is a need to connect Verilog-AMS digital components to VHDL-AMS analog components and vice versa.
Second, Verilog-AMS designs and the VHDL-AMS designs are represented differently. Verilog-AMS designs are represented as flattened designs. On the other hand, VHDL-AMS designs are represented as hierarchical designs.
Third, the Verilog-AMS language and the VHDL-AMS language use different semantics for describing a port direction. As a result, drivers in Verilog-AMS and VHDL-AMS are treated differently. Information about the digital drivers from other hierarchical VHDL-AMS levels may not be available at the same time as those from Verilog-AMS. These differences add to the challenges of implementing DRS in an MLMS design.
In summary, there is a need for using previously designed components from both Verilog-AMS and VHDL-AMS languages and taking advantages of the benefits from both languages. The existing workarounds are inflexible and suffer a number of limitations. Therefore, there is a need for implementing the DRS techniques in an MLMS environment that can provide flexible and automated solutions for integrating design components from both Verilog-AMS and VHDL-AMS languages seamlessly.